USBDIV=THE_DIVIDER_IS_TURNE, USBSEL=SYSCLK
USB Clock Selection register
| USBDIV | Selects the divide value for creating the USB clock from the selected PLL output. Only the values shown below can produce even number multiples of 48 MHz from the PLL. Warning: Improper setting of this value will result in incorrect operation of the USB interface. Only the main oscillator in conjunction with either PLL0 or PLL1 can provide a clock that meets USB accuracy and jitter specifications. Other values cannot produce the 48 MHz clock required for USB operation. 0 (THE_DIVIDER_IS_TURNE): The divider is turned off, no clock will be provided to the USB subsystem. 4 (PLL0_OUTPUT_IS_DIVID): PLL0 output is divided by 4. PLL0 output must be 192 MHz. 6 (PLL0_OUTPUT_IS_DIVID): PLL0 output is divided by 6. PLL0 output must be 288 MHz. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| USBSEL | Selects the input clock for the USB clock divider. 0 (SYSCLK): Sysclk is used as the input to the USB clock divider. When this clock is selected, the USB can be accessed by software but cannot perform USB functions. 1 (MAINPLLOUT): The output of the Main PLL is used as the input to the USB clock divider. 2 (ALTPLLOOUT): The output of the Alt PLL is used as the input to the USB clock divider. 3 (RESERVED): Reserved, this setting should not be used. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |